Low-temperature back-end-of-line technology compatible with III-V nanowire MOSFETs
We present a low-temperature processing scheme for the integration of either lateral or vertical nanowire (NW) transistors with a multilayer back-end-of-line interconnect stack. The nanowire device temperature budget has been addressed, and materials for the interconnect fabrication have been selected accordingly. A benzocyclobutene (BCB) polymer is used as an interlayer dielectric, with interconn