Energy efficiency in Sub-VT of various 16-bit adder structures in 65 nm CMOS
This manuscript presents simulation results of energy dissipation in sub-threshold (sub-VT ) of various 16-bit adder structures. The architectures designed for the comparative experiments are, a bit-serial, an 8-bit digit-serial and a 16-bit parallel adder structures. The designs are synthesized in a 65 nm low-leakage high-threshold CMOS technology. The results show that an energy minimum operatin