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This paper evaluates the hardware aspects of multicarrier faster-than-Nyquist (FTN) signaling transceivers. The choice of time-frequency spacing of the symbols in an FTN system for improved bandwidth efficiency is targeted towards efficient hardware implementation. This work proposes a hardware architecture for the realization of iterative decoding of FTN multicarrier modulated signals. Compatibil

This paper presents an analysis of energy dissipation of a decimation filter chain of four half band digital (HBD) filters operated in the sub-threshold (sub-VT) region with throughput constraints. To combat speed degradation due to scaling of supply voltage, various HBD filters are implemented as unfolded structures. The designs are synthesized in 65 nm CMOS technology with low-power and three th

Defect management is a central task in software maintenance. When a defect is reported, appropriate resources must be allocated to analyze and resolve the defect. An important issue in resource allocation is the estimation of Defect Resolution Time (DRT). Prior research has considered different approaches for DRT prediction exploiting information retrieval techniques and similarity in textual defe

This paper presents a low latency, high throughput soft-output signal detector for a 4x4 64-QAM spatial-multiplexing MIMO system. To achieve high data-level parallelism and accurate soft information, the detector adopts a channel-adaptive node perturbation technique to generate a list of candidate vectors around an initial linear estimation. The detection algorithm provides a large range and conve

In telecommunication networks based on the current Ethernet technology, routing of traffic demands is based on multiple spanning trees: the network operator configures different routing spanning trees and assigns each demand to be routed in one of the selected spanning trees. A major optimization issue in this solution is the combined determination of (i) a set of appropriate spanning trees, and (

This paper presents the VLSI design of an energy-efficient, high-throughput soft-input soft-output signal detector for iterative multiple-input multiple-output (MIMO) receiver. The detector is evolved from our previously developed imbalanced fixed complexity sphere decoder and adopts several new algorithm-level techniques to exploit the available a priori information of transmitted bits. More spec

This paper describes a hardware efficient linear pre-coder for Massive MIMO Base Stations (BSs) comprising a very large number of antennas, say, in the order of 100s, serving multiple users simultaneously. To avoid hardware demanding direct matrix inversions required for the Zero-Forcing (ZF) pre-coder, we use low complexity Neumann series based approximations. Furthermore, we propose a method to

Background. In formal experiments on software engineering, the number of factors that may impact an outcome is very high. Some factors are controlled and change by design, while others are are either unforeseen or due to chance. Aims. This paper aims to explore how context factors change in a series of for- mal experiments and to identify implications for experimentation and replication practices

This paper presents a 1MHz bandwidth, ΔƩ fractional-N PLL as the frequency synthesizer for LTE. A noise cancellation path composed of a novel hybrid ΔƩ DAC with 9 output bits is incorporated into the PLL in order to cancel the out-of-band phase noise caused by the quantization error. Further, a re-timing circuit is proposed to reduce the nonlinearity in the Charge Pump and provide pulse shaping si

Weak alignment of requirements engineering (RE) with verification and validation (VV) may lead to problems in delivering the required products in time with the right quality. For example, weak communication of requirements changes to testers may result in lack of verification of new requirements and incorrect verification of old invalid requirements, leading to software quality problems, wasted ef

Pathloss is typically modeled using a log-distance power law with a large-scale fading term that is log-normal. However, the received signal is affected by the dynamic range and noise floor of the measurement system used to sound the channel, which can cause measurement samples to be truncated or censored. If the information about the censored samples is not included in the estimation method, as i

Families of generalized spatially-coupled low-density parity-check (GSC-LDPC) code ensembles can be formed by terminating protograph-based generalized LDPC convolutional (GLDPCC) codes. It has previously been shown that ensembles of GSC-LDPC codes constructed from a protograph have better iterative decoding thresholds than their block code counterparts, and that, for large termination lengths, the

The Theory of Characteristic Modes provides a convenient tool for designing multi-antennas for MIMO applications, as it enables orthogonal radiation patterns to be excited in a given antenna structure. Moreover, the frequency behavior of the modes reveals interesting wideband properties of the structure. However, the tracking of characteristic modes over frequency remains a challenge, especially w

This paper presents an energy-efficient sorted QR decomposition (SQRD) processor for 3GPP LTE-Advanced (LTE-A) systems. The processor adopts a hybrid decomposition scheme to reduce computational complexity and provides a wide-range of performance complexity trade-offs. Based on the energy distribution of spatial channels, it switches between the brute-force SQRD and a low-complexity group-sort QR-

The 14th edition of International Telecommunications Network Strategy and Planning Symposium (shortly: Networks 2010) held in Warsaw, Poland. Networks 2010 was a four-day professional and scientific event organized by Warsaw University of Technology in co-operation with Polish Association of Telecommunication Engineers (SIT). The conference was focused on network design and planning methods includ

In this paper a frequency compensation method for operational transconductance amplifiers is proposed, which poses no power overhead compared to Miller compensation, while improving the 3dB bandwidth, the unity gain frequency and the slew rate. The technique employees positive feedback to introduce an extra left half plane zero to cancel a pole.The phase margin shows good robustness against proces

This paper presents a multi-bit, continuous time delta-sigma modulator with 20 MHz bandwidth implemented in 65nm CMOS for cellular communication. The modulator features a third order, single loop filter and a 4-bit internal quantizer operating at 640 MHz. The DACs are resistive for lower thermal noise compared to the current-steering DACs and nonreturn-to-zero DAC pulse is used to reduce the clock