A 65-nm CMOS Area Optimized De-synchronization Flow for sub-V-T Designs
This paper proposes a process independent post layout de-synchronization flow implemented in tool command language working on designs operating in the sub-V-T regime. The overhead due to the self-timed operation is combated by introducing full-custom delay elements and latches for a standard 65-nm CMOS process. The flow offers the possibility to adjust granularity based on user requirements. Case
