A VLSI architecture of the Schnorr-Euchner decoder for MIMO systems
The lattice decoder is shown to approach the performance of Maximum-likelihood decoder for MIMO wireless systems with low complexity. A VLSI architecture of the K-best Schnorr-Euchner lattice decoder is proposed in this paper. The architecture is optimized on both algorithm and architecture levels, and supports a dynamic range of SNR [less-than or equal to] 30 dB. Compared to a conventional VLSI i
