A 12b, 1 GSps TI pipelined-SAR converter with 65 dB SFDR through buffer linearization and gain mismatch correction in 28nm FD-SOI
This paper presents a time-interleaved pipelined-SAR converter targeting a multi-band mobile communication receiver. The input buffer is based on a super-source follower and linearized by selecting a specific bias current and drain bias resistor. Time interleaved sampling time mismatch is resolved by using a common sample and hold circuit, and gain mismatch is corrected by fine tuning respective s
