A 700-MHZ 24-bit pipelined accumulator in 1.2-um CMOS for application as a numerically controlled oscillator
To accomplish timing recovery/synthesis in high-speed communication systems, a 24-b numerically controlled oscillator (NCO) IC using a circuit design technique called true single-phase clock (TSPC) pipelined CMOS has been fabricated in a standard 1.2-μm CMOS process. The device achieves a maximum tested input clock rate of 700 MHz, which results in an output frequency tuning range from DC up to 35