Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
Theever-increasing test data volume for core-based system-on-chip(SOC) integrated circuits is resulting in high test times andexcessive tester memory requirements. To reduce both test time andtest data volume, we propose a technique for test-architectureoptimization and test scheduling that is based on core-levelexpansion of compressed test patterns. For each wrapped embeddedcore and its decompres
