A digitally controlled PLL for SoC applications
A fully integrated digitally controlled phase-locked loop (PLL) used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. The design is, therefore, portable between technologies as an IP block. Using a 0.35-mum standard CMOS process and a 3.0-V supply voltage, the PLL has a fr
