VHDL vs. Bluespec System Verilog: A case study on a Java embedded architecture
This paper compares two hardware design flows, based on the classic VHDL on one side and the relatively new Bluespec System Verilog (BSV) on the other side. The comparison is based on a case study of a Java embedded architecture, comprising a Java native processor and a memory management unit. The processor is a micro-programmed, pipelined, Java-optimized processor (JOP), initially written in VHDL
