Spice Circuit Reduction for Speeding up Simulation and Verification
The focus of this work has been to implement a generic netlist reduction engine to speed up circuit simulations. The netlist reduction techniques are further optimized for Static Random-Access Memory (SRAM), wherein we exploit the repetitive pattern of the circuit. There are many driving factors for developing a netlist reduction engine for SRAM simulations. In today's System on Chip (SoC), S
